Not Just Chips: Signal Integrity Analysis at the Dawn of the Interposer Era
Signal Integrity Analysis at the Dawn of the Interposer Era
Matt Commens
Kelly Damalou
Ansys
The development of applications like high-performance computing (HPC), bespoke Artificial Intelligence (AI) processors, along with advancements in Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips often involves the use of 2.5D/3D IC technology which necessitate advanced packaging approaches. Achieving the aggressive and desired performance goals can radically alter traditional design methodologies and flows. Designers of high-speed components are now expected to co-simulate die, interposer and package, even printed circuit boards (PCB), to validate designs and sign-off for the signal integrity (SI) of their products with high confidence.
Signal Integrity is standard in analyzing ICs or PCBs, but in the case of silicon interposers a new set of challenges emerge. The combination of silicon density and very high speeds, novel large-scale physics such as through-silicon vias (TSVs) and interposer capacitors, and high-speed signaling over multiple millimeters – orders of magnitude longer than on-chip interconnects, push traditional solutions to their boundaries.
Team dynamics are also a big challenge during design and signoff. Different groups have traditionally collaborated only late in the development cycle. But designing the silicon first and throwing it “over the wall” to package and board designers will not result in design convergence on an optimal, cost-effective solution.
This presentation will explore Ansys multiphysics, advanced workflows and powerful electromagnetic solvers uncovering and helping address SI issues for the most complex silicon interposer architecture, and address the challenges with advanced packaging architectures, thus increasing the confidence of the signoff process and the success of new 2.5D/3D-ICs products.
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