CICC EDUCATIONAL SESSION - Low-Spur PLL Architectures and Techniques - Mike Shuo-Wei Chen
ES2-3
Low-Spur PLL Architectures and Techniques
Mike Shuo-Wei Chen, University of Southern California
One key design objective of a frequency synthesizer is to minimize the spurious tones, as they can degrade the overall jitter performance or cause other unwanted system-level impairments. In this tutorial, we will examine the sources of the spurious tone generation in different PLL architectures and operation modes. We will overview several design techniques to mitigate the spurious tones. Lastly, we will go over several real PLL design examples that demonstrate low-spur performances.
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