Power integrity for printed circuit board design by James L. Drewniak
Straight from Dgcon 2017 - The Main Signal & Power Integrity Event In Israel!
http://www.dgcon.info/
Initiated by Dgtronix, Dgcon is the first Israeli conference targeted to provide the necessary technical knowledge, covering many aspects of Hardware Design.
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The Lecture:
Power integrity in high-speed digital designs is among the significant design challenges for high data rate and high speed systems. Best engineering practices for design of a power distribution network at the package and PCB level are well known. In practice this comes down to minimizing inductance over the current-draw path. However, there are many subtle design choices that can impact achieving a minimal power net voltage ripple or meeting a target impedance specification. In order to achieve a best design with or without constraints on some of these choices, a proven methodology for calculating the portions of inductance associated with particular geometry features is necessary, and a knowledge of inductance physics that can be exploited to achieve the design specification within a given stackup and a minimal number of decoupling capacitors.
A systematic methodology has been developed for PDN design and PI analysis that can readily identify a best design given typical design constraints. A method for PDN impedance calculation will be shown, and approach for achieving a target impedance will be given. If the target impedance specification is not met, the developed methodology can be used to immediately identify if specifications can be met with design modifications within the constraints, and provide directions in doing so in one or two iterations while avoiding trial-and-error simulations.
The Expert:
James L. Drewniak is a Curator’s Professor of Electrical and Computer Engineering at Missouri S&T, and with the Electromagnetic Compatibility Laboratory. He received B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign. His research is in electromagnetic compatibility, signal and power integrity, and electronic packaging. He leads a university research laboratory of 65 people that is internationally recognized for research in EMC and signal and power integrity, with funding that has included government and industry sources. A key research funding component is the NSF Industry/University Cooperative Research Center (I/UCRC) for Electromagnetic Compatibility that is a consortium of approximately 20 companies, with over 20 funded projects. He is a Fellow of the IEEE, 2013 recipient of the IEEE EMC Society’s Richard R. Stoddart Award, and a past Associate Editor of the IEEE Transactions on EMC.
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