A step by step Guide for channel modeling and simulation by Amiram Jibly & Alex Manukovsky
Straight from Dgcon 2017 - The Main Signal & Power Integrity Event In Israel!
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Initiated by Dgtronix, Dgcon is the first Israeli conference targeted to provide the necessary technical knowledge, covering many aspects of Hardware Design.
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The Lecture:
A step by step Guide for channel modeling and simulation that correlate to lab measurement for 25Gb NRZ and 56Gb PAM4 applications.
Predictive channel simulation becomes a challenging task as frequencies increase and compliance requirements become stricter. This work presents a step by step practical guide on the modeling and simulation of high-speed channels achieving a tight correlation to lab measurement for 25 Gb NRZ and 56 Gb PAM4 application. We will present a case study to provide an insight on how to correctly model each channel segment with respect to its main effect in the post layout simulation process. We will discuss common pitfalls in modeling, and go over manufacturing considerations. We will survey the required lab measurements for enabling correlation work and measurement based modeling.
The Experts:
Alex Manukovsky is a Technical lead, of the Signal & Power Integrity team at Intel Networking Division, responsible for the development of indoor link simulator for high speed serial links, combining both traditional methods of frequency and time domain simulation along with AI machine learning capabilities. Alex focuses on simulation to lab correlation for high speed serial links for PCIe and Ethernet technologies and AI. His past work focused on channel modeling, robust deembedding and calibration techniques for VNA and TDR. His experience includes developing test equipment for compliance testing of serial I/O’s as well as lab measurement methodologies for volume testing and Si/Pi simulations. Alex joined Intel in 2010 after receiving his BSc in Electrical Engineering from the Technion – Israel Institute of Technology. He is currently pursuing his Master’s degree in System Engineering from the Technion – Israel Institute of Technology.
Amiram Jibly is a System Design Technical lead at the Network ASIC group at Intel, has been with Intel in the last 7 years and is experienced in package and board design for high speed systems.
His current work focuses on passive interconnect simulation for 56G interfaces as well as design for 25G and 56G electrical validation systems.
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