Stanford Seminar - Dynamic Code Optimization and the NVIDIA Denver Processor
"Dynamic Code Optimization and the NVIDIA Denver Processor" - Nathan Tuck of NVIDIA
Colloquium on Computer Systems Seminar Series (EE380) presents the current research in design, implementation, analysis, and use of computer systems. Topics range from integrated circuits to operating systems and programming languages. It is free and open to the public, with new lectures each week.
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0:00 Introduction
1:19 TEGRA K1 with Dual Denver CPUs
2:58 DENVER VALUE PROPOSITION
6:40 PIPELINE SKEW
8:09 SKEWED PIPELINE
9:03 Pipeline Microarchitecture - Mispredict Penalty
9:37 DENVER PERFORMANCE
12:56 IDEALISTIC VIEW OF CPU DESIGN
14:38 CYNICAL VIEW OF CPU DESIGN
16:13 HW VS SW IN MICROARCHITECTURE
19:15 DCO VIEW OF CPU DESIGN
24:30 DCO UARCH SIMPLIFICATIONS
25:37 DYNAMIC CODE OPTIMIZATION OPTIMIZE ONCE, USE MANY TIMES
42:44 186.CRAFTY EXECUTION -3% of benchmark run
45:24 CODE EXAMPLE FROM 164.GZIP
59:43 HISTORICAL BT SYSTEMS
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