Abstract- CMOS scaling remains economically lucrative with 7nm mobile SoCs already commercialized in late 2018 and 5nm products on the horizon. Modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next node. With design/technology co-optimization tailored to logic and SRAM, analog/mixed-signal circuits do not fully enjoy these benefits. Instead, they experience more time-consuming design closure, facing worse parasitic resistance and capacitance, stronger layout-dependent effects, and poor area scaling. This talk provides an overview of the key process technology elements (not just finFETs) enabling the advanced CMOS nodes and highlights the impact of the resulting technology on analog/mixed-signal design. Some design strategies, such as technology-aware analog design cells, are offered to address these challenges and improve design efficiency.
Bio- Alvin Loke has worked on CMOS technology and design since 1998 and volunteered in the IEEE Solid-State Circuits Society (SSCS) since 2003. He holds a BASc in engineering physics from the University of British Columbia, and MS and PhD in electrical engineering from Stanford University. He spent several years in CMOS process integration at HP Labs and Chartered Semiconductor (as an Agilent assignee) before shifting to wireline design and design/technology interfacing at Agilent, AMD, and Qualcomm. Alvin recently joined the newly formed TSMC San Diego Design Center to work on next-generation CMOS analog/mixed-signal design/technology co-optimization. He has authored over 50 publications (including a CICC 2018 Best Paper) and 25 US patents. He is currently a VLSI Symposia committee member, the SSCS North America Webinar Coordinator, and San Diego SSCS Chapter Chair. Alvin has previously served as a SSCS Distinguished Lecturer (2012-2013), CICC committee member (2006-2012), Fort Collins SSCS Chapter officer (2003-2013), and guest editor of JSSC and SSCL.
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