RISC V processor verification with new open standard RVVI based methodology
Speaker: Simon Davidmann, Imperas Software
Speaker Biography: Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) – the place for Fast Processor Models. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit, which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.
Abstract: RISC-V is extending the design freedoms for SoC developers with an open standard ISA. RISC-V is based on a modular framework with many standard extensions plus further optimization with custom instructions.
Recorded at: DVClub Europe Conference 2022
Date: 29th November 2022
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