Parity Generator and Parity Checker in tamil
Parity Generator and Parity checker
A parity generator and a parity checker are two digital circuits commonly used in computer systems to detect and correct errors in data transmission.
A parity generator is a digital circuit that takes an input stream of data bits and generates an additional parity bit, which is used to check for errors during transmission. The parity bit is usually added to the end of the data stream and can be either even or odd. In even parity, the parity bit is set to 1 if the number of 1's in the data stream is odd. In odd parity, the parity bit is set to 1 if the number of 1's in the data stream is even.
A parity checker, on the other hand, is a digital circuit that takes the transmitted data stream and the corresponding parity bit and checks whether the data has been corrupted during transmission. The parity checker counts the number of 1's in the data stream and compares it to the expected parity bit value. If the number of 1's is even and the parity bit is set to even parity, or if the number of 1's is odd and the parity bit is set to odd parity, then the data is considered to be error-free. If the parity check fails, it means that the data has been corrupted during transmission and needs to be re-transmitted or corrected.
Parity generators and checkers are simple and inexpensive circuits that can detect errors in data transmission with a high degree of accuracy. However, they are not foolproof and can only detect certain types of errors. For example, they cannot detect errors that involve two or more bit errors in the data stream. Therefore, more advanced error detection and correction techniques, such as cyclic redundancy checks (CRC), are often used in modern computer systems.
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