Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
Featuring: Joe Hupcey III, Gabriel Chidolue, Jonathan Lovett, Shantanu Samant
In this interview the presenters of the DVCon USA 2016 tutorial, “Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs” talk about the latest advances in low power design&verification introduced in the UPF 3.0 standard, and how it enables bit IP creators and IP customers to simplify their D&V flows.
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