Test 2 3 6 SIMD Control Flow

Test 1 5 4 Basic Cache Optimizations to Reduce Miss Rate

Test 1 5 8 Give Priority to Read Misses

Test 2 4 6 Examples of Interleaved Multithreading

Test 1 5 3 Hit or Miss Example

1 2 2 MIPS64 Addressing Modes and Instruction Formats

Test 1 5 7 Reduce Miss Penalty by Multilevel Cache

Test 1 5 1 Caches and the Principle of Locality

Test 2 3 4 Special Purpose Instructions & Data Conversions

1 2 3 MIPS64 Operations

Test 2 3 3 SIMD Multiplication Instructions

Test 2 3 1 Introduction to SIMD

1 1 5 CPU Performance Equation

Test 1 5 6 Cache Metrics and Improving AMAT

Test 2 4 5 Introduction to Interleaved Multithreading

1 3 1 Pipelining Principles

1 3 3 MIPS Pipeline Features and Pipeline Hazards

Test 1 5 5 Cache Equations for Set Associative Caches

Test 1 5 2 Direct mapped Cache Organization

Test 2 4 3 Introduction to Block Multithreading

Test 2 3 2 SIMD Register File, Data Types, and Instructions

Test 2 3 6 SIMD Control Flow

Test 2 3 5 Data Alignment and Reordering

Test 2 4 1 TLP Motivation and Introduction

Test 2 4 2 SW and HW Multithreading